Semiconductor - Products - Programmable Logic

Because today's product life cycles are so brief, time to production becomes essential, which means that programmable logic assumes a more critical role than ever in the rapid prototyping of products and moving them quickly into full production.

Avnet Electronics Marketing's comprehensive portfolio of programmable logic products provide a broad selection of options to choose from - in fact we carry 5 of the top 7 manufacturers worldwide.*

Additionally, we also support associated design requirements through Avnet Design Services. ADS offers a suite of focused engineering and technical srvices ranging from simple component evaluation and recommendation to code writing to full turnkey engineering and custom ASIC design.

Simply click on any of the following links to easily select and source your programmable logic needs and keep current on the latest technology, packaging and market trends.

* Source: Semico Research Corp

[Click Here for the Programmable Logic Resource Page]

A [BACK TO TOP]
ABEL- Advanced Boolean Expression Language, low-level language for design entry, from Data I/O.

AHDL- Altera-proprietary high-level language for design entry.

Antifuse- A small circuit element that can be irreversibly changed from being non-conducting to being conducting with ~100 Ohm. Anti-fuse-based FPGAs are thus non-volatile and can be programmed only once (see OTP).

AQL- Acceptable Quality Level. The relative number of devices, expressed in parts-per-million, that might not meet specification or be defective. Typical values are around 10 ppm.

ASIC- Applications-Specific Integrated Circuit, also called a gate array Asynchronous Logic that is not synchronized by a clock. Asynchronous designs can be faster than synchronous ones, but are more sensitive to parametric changes, and are thus less robust.

ATM- Asynchronous Transfer Mode. A very-high-speed (megahertz to gigahertz) connection-oriented bit-serial protocol for transmitting data and real-time voice and video in fixed-length packets (48-byte payload, 5-byte header).

B [BACK TO TOP]
Back annotation- Automatically attaching timing values to the entered design format after the design has been placed and routed in an FPGA.

Behavioral language- Top-down description from an even higher level than VHDL.

Block RAM- A block of 2k to 4k bits of RAM inside an FPGA. Dual-port and synchronous operation are desirable.

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CAD Computer- Aided Design, using computers to design products.

CAE Computer- Aided Engineering, analyzes designs created on a computer.

CLB- Configurable Logic Block. Xilinx-specific name for a block of logic surrounded by routing resources. A CLB contains 2 or 4 look-up-tables function generators) plus 2 or 4 flip-flops.

CMOS- Complementary Metal-Oxide-Silicon. Dominant technology for logic and memory. Has replaced the older bipolar TTL technology in most applications except very fast ones. CMOS offers lower power consumption and smaller chip size compared to bipolar and now meets or even beats TTL speed.

Compiler- software that converts a higher-language description into a lower-level representation. For FPGAs : the complete partition, place & route process.

Configuration- The internally stored file that controls the FPGA so that it performs the desired logic function. Also: The act of loading an FPGA with that file.

Constraints- Performance requirements imposed on the design, usually in the form of max allowable delay, or required operating frequency.

CPLD- Complex Programmable Logic Device, synonymous with EPLD. PAL-derived programmable logic devices that implement logic as sum-of-products driving macrocells. CPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have relatively high power consumption and fewer flip-flops, compared to FPGAs.

CUPL- Compiler Universal for Programmable Logic, CPLD development tool available from Logical Devices.

D [BACK TO TOP]
Debugging- The process of finding and eliminating functional errors in software and hardware.

Density- Amount of logic in a device, often used to mean capacity. Usually measured in gates, but for FPGAs better expressed in Logic Cells, each consisting of a 4-input look-up table and a flip-flop.

Down- binning- Marking and selling a fast part as a slower part, when the market demand pattern makes that necessary.

DRAM- Dynamic Random Access Memory. A low-cost\read-write memory where data is stored on capacitors and must be refreshed periodically. DRAMs are usually addressed by a sequence of two addresses, row address and column address, which makes them slower and more difficult to use than SRAMs.

DSP- Digital Signal Processing. The manipulation of analog data that has been sampled and converted into a digital representation. Examples are: filtering, convolution, Fast-Fourier-Transform, etc.

E [BACK TO TOP]
EAB- Embedded Array Block. Altera name for Block RAM in FLEX10K.

EDIF- Electronic Data Interchange Format. Industry-standard for specifying a logic design in text (ASCII) form.

EPLD- Erasable Programmable Logic Devices, synonymous with CPLDs. PAL-derived programmable logic devices that implement logic as sum-of-products Driving macrocells. EPLDs are known to have short pin-to-pin delays, and can accept wide inputs, but have relatively high power consumption and fewer flip-flops than FPGAs.

Embedded RAM- Read-write memory stored inside a logic device. Avoids the delay and additional connections of an external RAM. ESD- Electro-Static discharge. High-voltage discharge can rupture the input transistor gate oxide.

ESD-protection diodes divert the current to the supply leads.

F [BACK TO TOP]
5-volt tolerant- Characteristic of the input or I/O pin of a 3.3 V device that allows this pin to be driven to 5 V without any excessive input current or device breakdown. Very desirable feature.

FIFO- First-In-First-Out memory, where data is stored in the incoming sequence, and is read out in the same sequence. Input and output can be Synchronous to each other. A FIFO needs no external addresses, although all modern FIFOs are implemented internally with RAMs driven by circular read and write counters.

FIT- Failure In Time. Describes the number of device failures statistically expected for a certain number of device-hours. Expressed as failures per one billion device hours. Device temperature must be specified. MTBF can be calculated from FIT.

Flash- Nonvolatile programmable technology, an alternative to Electrically-Erasable Programmable Read-Only Memory (EEPROM) technology. The memory content can be erased by an electrical signal. This allows in-system programmability and eliminates the need for ultraviolet light and quartz windows in the package.

Flip-flop- Single-bit storage cell that samples its Data input at the active (rising or falling ) clock edge, and then presents the new state on its Q output after that clock edge, holding it there until after the next active clock edge.

Floorplanning- Method of manually assigning specific parts of the design to specific chip locations. Can achieve faster compilation, better Utilization, and higher performance.

Footprint- The printed-circuit pattern that accepts a device and connects its pins appropriately. Footprint-compatible devices can be interchanged without modifying the pc-board.

FPGA- Field Programmable Gate Array. An integrated circuit that contains configurable (programmable) logic blocks and configurable (programmable) interconnect between these blocks.

Function Generator- Also called look-up-table (LUT), with N-inputs and one output. Can implement any logic function of its N-inputs. N is between 2 and 6, most popular are 4-input function generators.

G [BACK TO TOP]
GAL- Generic Array Logic. Lattice name for a variation on Pals Gate Smallest logic element with several inputs and one output. AND gate output is High when all inputs are High. OR gate output is High when at least one input is High. A 2-input NAND gate is used as the measurement unit for gate array complexity.

Gate Array- ASIC where transistors are pre-defined, and only the interconnect pattern is customized for the individual application.

GUI- Graphic User Interface. The way of representing the computer output on the screen as graphics, pictures, icons and windows. Pioneered by Xerox and the Macintosh, now universally adopted, e.g by Windows95.

H [BACK TO TOP]
HardWire- Xilinx name for a low-cost derivative of an FPGA, where the configuration is fixed, but functionality and footprint are identical with the original FPGA-based design.

HDL- Hardware Description Language.

Hierarchical design- Design description in multiple layers, from the highest ( overview) to the lowest (circuit details). Alternative: Flat design, where everything is described at the same level of detail. Incremental design Making small design changes while maintaining most of the lay-out and routing.

I [BACK TO TOP]
Interconnect- Metal lines and programmable switches that connect signals between logic blocks and between logic blocks and the I/O.

IOB or I/O- Input/Output Block. Logic block with features specialized for interfacing with the PC-board

IP- Intellectual Property. In the legal sense: Patents, copyrights and trade secrets. In integrated circuits: predefined large functions, called cores, that help the user complete a large design faster.

ISO9000- An internationally recognized quality standard. Xilinx is certified to ISO9001 and ISO9002.

ISP- In-System Programmable device. A programmable logic device that can be programmed after it has been connected to (soldered into ) the system PC-board Although all SRAM-based FPGAs are naturally ISP, this term is only used with certain CPLDs, to distinguish them from the older CPLDs that must be programmed in programming equipment.

J [BACK TO TOP]
JTAG- Joint Test Action Group. Older name for IEEE 1149.1 boundary scan, a method to test pc-boards and also ICs.

L [BACK TO TOP]
LAB- Logic Array Block. Altera name for a group of eight Logic Elements.

LogiBLOX- Formerly called X-Blox. Library of logic modules, often with user-definable parameters, like data width. Very similar to LPM.

Logic Cell- Metric for FPGA density. One logic cell is one 4-input lookup table plus one flip-flop.

LPM- Library of Parametrized Modules, library of logic modules, often with user-definable parameters, like data width. Very similar to LogiBlox.

LUT- Look-Up-Table, also called function generator with N inputs and one output. Can implement any logic function of its N inputs. N is between 2 and 6, most popular are 4-input LUTs.

M [BACK TO TOP]
Macrocell- The logic cell in a sum-of-products CPLD or PAL/GAL.

Mapping- Process of assigning portions of the logic design to the physical chip resources ( CLBs ). With FPGAs, mapping is a more demanding and more important process than with gate arrays.

MTBF- Mean Time Between Failure. The statistically relevant up-time between equipment failure. See also FIT.

N [BACK TO TOP]
Netlist- Textual description of logic and interconnects. See XNF and EDIF.

NRE- Non-Recurring Engineering charges. Start-up cost for the creation of an ASIC, gate array, or Hardwire Pays for layout, masks, and test development. FPGAs and CPLDs do not require NRE.

O [BACK TO TOP]
Optimization- Design change to improve performance. See also: Synthesis.

OTP- One-Time Programmable. Irreversible method of programming logic or memory. Fuses and antifuses are inherently OTP. EPROMs and EPROM-based CPLDs are OTP if their plastic package blocks the ultraviolet light needed to erase the stored data or configuration.

P [BACK TO TOP]
PAL- Programmable Array Logic. Oldest practical form of programmable logic, implemented a sum-of-products plus optional output flip-flops.

Partitioning- In FPGAs, the process of dividing the logic into subfunctions that can later be placed into individual CLBs. Partitioning precedes placement.

pASIC- Quicklogic name for their antifuse-based FPGAs.

PCI- Peripheral Component Interface. Synchronous bus standard characterized by short range, light loading, low cost, and high performance. 33-MHz PCI can support data byte transfers of up to 132 megabytes per second on 36 parallel data lines ( including parity) and a common clock. There is also a new 66-MHz standard.

PCMCIA- Personal Computer Memory Card interface Association, also: People CanÕt Memorize Computer Industry Acronyms. Physical and electrical standard for small plug-in boards for portable computers.

Pin-locking- Rigidly defining and maintaining the functionality and timing requirements of device pins while the internal logic is still being designed or modified. Pin-locking has become important, since circuit-board-fabrication times are longer than PLD design implementation times.

PIP- Programmable Interconnect Point. In Xilinx FPGAs, a point where two signal lines can be connected, as determined by the device configuration.

Placement- In FPGAs, the process of assigning specific parts of the design to specific locations (CLBs) on the chip. Usually done automatically.

PLD- Programmable Logic Device. Most generic name for all programmable logic: Pals, CPLDs, and FPGAs.

Q [BACK TO TOP]
QML- Qualified Manufacturing Line. For example, ISO9000.

R [BACK TO TOP]
Routing- The interconnection, or the process of creating the desired interconnection, of logic cells to make them perform the desired function. Routing follows after partitioning and placement.

S [BACK TO TOP]
Schematic- Graphic representation of a logic design in the form of interconnected gates, flip-flops and larger blocks. Older and more visually intuitive alternative to the increasingly more popular equation-based or high-level language textual description of a logic design.

Select-RAM- Xilinx-specific name for a small RAM (usually 16 bits), implemented in a LUT.

Simulation- Computer modeling of logic and (sometimes) timing behavior of logic driven by simulation inputs (stimuli, or vectors).

SPROM- Serial Programmable Read-only Memory. Nonvolatile memory device that can store the FPGA configuration bitstream. The SPROM has a built-in address counter, receives a clock and outputs a serial bitstream.

SRAM- Static Random Access Memory. Read-write memory with data stored in latches. Faster than DRAM and with simpler timing requirements, but smaller in size and about 4-times more expensive than DRAM of the same capacity.

Static timing- Detailed description of on-chip logic and interconnect delays.

Submicron- The smallest feature size is usually expressed in micron (µ= millionth of a meter, or thousandth of a millimeter) The state of the art is moving from 0.35µ to 0.25µ, and may soon reach 0.18µ. The wavelength of visible light is 0.4 to 0.8µ. 1 mil = 25.4µ.

Synchronous- Circuitry that changes state only in response to a common clock, as opposed to asynchronous circuitry that responds to a multitude of derived signals. Synchronous circuits are easier to design, debug, and modify, and tolerate parameter changes and speed upgrades better than asynchronous circuits.

Synthesis- Optimization process of adapting a logic design to the logic resources available on the chip, like look-up-tables, Longline, dedicated carry. Synthesis precedes Mapping.

T [BACK TO TOP]
TBUFs- Buffers with a 3-state option, where the output can be made inactive. Used for multiplexing different data sources onto a common bus. The pull-down-only option can use the bus as a wired AND function.

Timing- Relating to delays, performance, or speed.

Timing driven- A design or layout method that takes performance requirements into consideration. Compiled by Peter Alfke, September 1997

U [BACK TO TOP]
UART- Universal Asynchronous Receiver/Transmitter. An 8-bit-parallel-to-serial and serial-to-8-bit-parallel converter, combined with parity and start-detect circuitry and sometimes even FIFO buffers. Used widely in asynchronous serial-communications interfaces, (e.g. modems).

USB- Universal Serial Bus. A new, low-cost, low-speed, self-clocking bit-serial bus (1.5 MHz and 12 MHz) using 4 wires (Vcc, ground, differential data) to daisy-chain up to 128 devices.

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VME- Older bus standard, popular with MC68000-based industrial computers.

X [BACK TO TOP]
XABEL- Xilinx-specific version of the ABEL design-entry software.

XNF File- Xilinx-proprietary description format for a logic design Alternative: EDIF).